holding the previous output.Ĭase 2: When S=1 and R=0 then Q’ becomes 1 and since Q’=1 and S=1 then Q goes to 0, putting the latch in the Reset state and both the outputs Q and Q’ are complement to each other. Now when the S input goes back to 1, the circuit remains in the set state, which means when S=1 and R= 1, the latch is in memory state i.e. The SR latch using two cross-coupled NAND gates is shown in Fig.2.Ĭase 1: When S=0 and R=1 then by using the property of NAND gate (if one of the inputs to the gate is 0 then the output is 1), therefore Q becomes 1 as S=0, putting the latch in the Set state and now since Q= 1 and R=1 then Q’ becomes 0, hence Q and Q’ are complement to each other. The truth table of SR NOR latch is given below S In normal operation, this condition is avoided by making sure that 1’s are not applied to both the inputs simultaneously. S=0 and R=0 is the memory or hold state which means latch is holding or storing the previous output.Ĭase 3: When S=1 and R= 1, then both the outputs Q and Q’ becomes 0 by using the property of NOR gate, which violates the requirement that both the outputs must be complement of each other. Similarly, if S goes back to 0, then the circuit will remain in the set state, i.e. S=0 and R= 0, then let if Q’ =1 then again by using the property of NOR gate Q becomes 0, it seems we get the previous output which gets stored in the latch, therefore S=0 and R=0 are called as memory condition.Ĭase 2: When S=1 and R=0, then by using the property of NOR gate, we get Q’ =0 and now if R=0 and Q’ =0 then Q becomes 1 which is the condition for the Set state. These changes occur because the circuit is using NOR gates instead of NAND. They have also changed places, the R input is now on the gate having the Q output and the S input is on the Q gate. Now if R goes back to 0, the circuit remains in the Reset state i.e in another word if we remove the inputs i.e. In this circuit the S and R inputs have now become S and R inputs, meaning that they will now be ‘active high’. This is the Reset condition as output Q=0 when R=1. 1 SR Latch using NOR gateĬase 1: When S=0 and R=1, then by using the property of NOR gate (if one of the inputs to the gate is 1 then the output is 0), therefore the output Q=0 since R=1 and if Q=0 and S=0 then Q’ becomes 1, hence Q and Q’ are complement to each other. Normally, outputs Q and Q’ are complement to each other.
When Q= 0 and Q’=1, it is in Reset state. When output Q=1 and Q’= 0, the latch is said to be in the Set state. The SR latch constructed using two cross-coupled NOR gates is shown in Fig.1. The SR latch is a circuit with two cross-coupled NOR gates or two cross-coupled NAND gates with two inputs labelled S (for Set) and R (for Reset) and with two complementary outputs Q and Q’.